Kioxia has unveiled its 10th generation 332-layer 3D NAND flash memory technology, offering up to 33% better performance and enhanced bit density, interface speeds, and power efficiency compared to its 8th generation ICs.

The new technology features a CMOS directly Bonded to Array (CBA) and Toggle DDR6.0 interface, enabling a 4.8 GB/s NAND interface speed.

While the 322-layer design is not yet at the company's goal of a 1,000-layer 3D NAND by 2027, it still represents a significant advancement in bit density by 59% and power efficiency improvements.

➀ Samsung Electronics is releasing a 1Tbit 3D NAND flash memory with storage cell layers up to 400+ layers, achieving a memory density of 28.2Gbit/mm2 using TLC method.

➁ Kioxia and Western Digital's joint development team is reporting a 1Tbit 3D NAND flash memory with 332 layers, with a memory density of up to 29Gbit/mm2.

➂ SK Hynix has developed a 2Tbit 3D NAND flash memory with 321 layers, using QLC method multi-value storage.

➃ Samsung is currently developing the 9th generation 3D NAND with 286 layers and is working on 400-layer technology.

➅ Kioxia plans to mass-produce 3D NAND storage devices with over 1,000 layers by 2031.

➆ The journey towards 1,000-layer 3D NAND involves multiple improvements in manufacturing processes, including vertical, horizontal, and logical aspects.

➀ The chip industry is striving to increase the stack height of 3D NAND flash memory from 200 layers to 800 layers or more in the coming years to meet the endless demand for various types of memory.

➁ The additional layers will bring new reliability issues and a series of incremental reliability challenges, but the NAND flash memory industry has been steadily increasing the stack height over the past decade.

➂ The development direction of 3D NAND is from 500 to 1,000 layers. However, achieving so many layers is not just a matter of doing more of what we have been doing.